The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop of the semiconductor memory device.
In a system consisting of a plurality of semiconductor devices, a semiconductor memory device is used as an apparatus to store data. When data are required in a data processing unit, for example, the central processing unit (CPU) etc., the semiconductor memory device outputs data corresponding to an address signal which is inputted from an apparatus to demand the data, or stores the data in a location corresponding to the address signal provided from an apparatus.
As the working speed of the system consisting of semiconductor devices becomes faster and the semiconductor device is highly integrated, semiconductor memory devices are also required to read or store the data faster. In order to input/output the data at a high speed, a synchronous memory device, which receives a system clock signal and inputs/outputs the data in synchronization with the system clock signal, has been developed. However, since the synchronous memory device is not sufficient to satisfy the required data input/output speed, a DDR (Double Data Rate) synchronous memory device, in which the data are inputted or outputted in synchronization with both a falling edge and a rising edge of the system clock signal, has been developed.
Since the DDR synchronous memory device inputs/outputs the data at the falling edge and the rising edge of the system clock signal, it processes the two data during one period of the system clock signal. That is, the DDR synchronous memory device has to output the data at the falling edge or the rising edge of the system clock signal and it has to store the input data at the falling edge or the rising edge of the system clock signal. Particularly, the timing when the DDR memory device outputs the data is to be accurately synchronized with the falling or rising edge of the system clock signal. Accordingly, a data output circuit of the DDR memory device also outputs the data in synchronization with the falling edge or the rising edge of the system clock signal inputted to the memory device.
However, the system clock signal inputted to the memory device reaches the data output circuit with a delay time which is inevitably caused by a clock input buffer and a signal transmission line in the memory device. Therefore, when the data output circuit outputs the data in synchronization with the delayed system clock signal, an external circuit which receives the data from the semiconductor memory device can receive the undesired data which are not exactly synchronized with the falling edge and the rising edge of the system clock signal.
In order to solve the problem, the semiconductor memory device includes a DLL (delay locked loop) circuit to fix the delay of the clock signal. The DLL circuit is an apparatus for compensating for an amount of the delay in an internal circuit of the memory device since the system clock signal is inputted to the memory device until it is delivered to the data output circuit. The DLL circuit seeks out a delay time of the system clock signal which is caused by the clock input buffer and the signal transmission line in the semiconductor memory device and outputs the system clock signal delayed according to an amount of the measured delay time to the data output circuit. That is, using the DLL circuit, the system clock signal inputted to the memory device is transferred to the data output circuit in a state where the delay of the system clock signal is fixed. The data output circuit outputs the data in synchronization with a delay-locked clock signal and the external circuit recognizes the delayed output data from the DDR memory as an exact output data which is synchronized with the system clock signal.
In actual operation, a delay-locked clock signal, which is outputted from a DLL circuit before one period of the clock signal at the time of outputting the data, is delivered to an output buffer and the data are outputted in synchronization with the delivered delay-locked clock signal. Accordingly, the data are more rapidly outputted than the delay time of the system clock signal which is delayed by the internal circuit of the memory device. In view of the external circuit of the memory device, the data output is accurately synchronized with the rising edge and the falling edge of the system clock signal inputted to the memory device. In conclusion, the DLL circuit is an apparatus to find out a value to determine how fast the data are outputted in order to compensate for the delay of the system clock signal in the memory device.
FIG. 1 is a block diagram of a conventional semiconductor memory device. The conventional semiconductor memory device includes a clock buffer 11, a clock driver 15, a first replica model 16A, a second replica model 16B, a first DLL circuit 18A, a second DLL circuit 18B, a duty cycle correction circuit 20, a rising clock driver 21A and a falling clock driver 21B. The clock buffer 11 receiving and buffering external system clock signals CLK and CLKB outputs a rising clock signal RCLK. The clock driver 15 receives the rising clock signal RCLK and outputs a reference clock signal REFCLK. The first DLL circuit 18A receiving the reference clock signal RECLKR and a rising feedback clock signal FBCLKR outputs a clock signal which is produced by delaying the reference clock signal REFCLK for a predetermined time. The second DLL circuit 18B receiving the reference clock signal REFCLK and a falling feedback clock signal FBCLKF outputs a clock signal which is produced by delaying the reference clock signal REFCLK for a predetermined time. The duty cycle correction circuit 20 controls the duty cycle ratio of the output signals from the first DLL circuit 18A and the second DLL circuit 18B.
The first replica model 16A delays a clock signal FBCLK_PR outputted from the duty cycle correction circuit 20 by a modeling value and outputs the rising feedback clock signal FBCLKR. The second replica model 16B delays a clock signal FBCLK_PF outputted from the duty cycle correction circuit 20 by the modeling value and outputs the falling feedback clock signal FBCLKR. The rising clock driver 21A receives the clock signal FBCLK_PR outputted from the duty cycle correction circuit 20 and outputs a delay-locked rising clock signal RCLK_DLL whose delay is fixed. The falling clock driver 21B also receives the clock signal FBCLK_PF outputted from the duty cycle correction circuit 20 and outputs a delay-locked falling clock signal FCLK_DLL whose delay is fixed.
The first DLL circuit 18A outputs a clock signal, which is produced by delaying the reference clock signal REFCLK with a delayed clock signal of the reference clock signal REFCLK, to the duty cycle correction circuit 20. The second DLL circuit 18B outputs a clock signal, which is produced by delaying the reference clock signal REFCLK with a delayed clock signal of an inverted reference clock signal, to the duty cycle correction circuit 20. The reason why these two DLL circuits are employed is that it is necessary to match the duty cycle ratio of the delay-locked clock signals. The first DLL circuit 18A performs the delay locking operation based on the rising edge of the reference clock REFCLK. The second DLL circuit 18b performs the delay locking operation based on the falling edge of the reference clock REFCLK. As mentioned above, the delay locking operations are performed respectively and the duty cycle correction circuit 20 outputs a duty cycle corrected clock signal by mixing two clock signals outputted from the first and second DLL circuits 18A and 18B. Accordingly, as compared with the first DLL circuit 18A, the second DLL circuit 18B performs the locking operation with a time difference of a half (½) clock.
On the other hand, as the operating speed of the semiconductor memory device increases, the frequency of the system clock signal inputted to the memory device becomes higher. The time margin for the operation of the semiconductor memory device is decreased and the margin about the operation for making the clock signal whose delay is fixed is also more and more decreased. Particularly, since the second DLL circuit 18B operates with the time difference of the half clock being different from the first DLL circuit 18A, it is very difficult to perform an exact delay locking operation.